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<div class="header">
  <div class="headertitle"><div class="title">RCC_ClkInitTypeDef Struct Reference<div class="ingroups"><a class="el" href="group___s_t_m32_h7xx___h_a_l___driver.html">STM32H7xx_HAL_Driver</a> &raquo; <a class="el" href="group___r_c_c.html">RCC</a> &raquo; <a class="el" href="group___r_c_c___exported___types.html">RCC Exported Types</a></div></div></div>
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<p>RCC System, AHB and APB busses clock configuration structure definition.  
 <a href="#details">More...</a></p>

<p><code>#include &lt;<a class="el" href="stm32h7xx__hal__rcc_8h_source.html">stm32h7xx_hal_rcc.h</a>&gt;</code></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 id="header-pub-attribs" class="groupheader"><a id="pub-attribs" name="pub-attribs"></a>
Public Attributes</h2></td></tr>
<tr class="memitem:a93a53676a1cfc5b55b8b990e7ff4dac5" id="r_a93a53676a1cfc5b55b8b990e7ff4dac5"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a93a53676a1cfc5b55b8b990e7ff4dac5">ClockType</a></td></tr>
<tr class="memitem:a4ceff1fdbf423e347c63052ca2c1d7e1" id="r_a4ceff1fdbf423e347c63052ca2c1d7e1"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a4ceff1fdbf423e347c63052ca2c1d7e1">SYSCLKSource</a></td></tr>
<tr class="memitem:aa49663a5d76af14424c7d1c3525b9381" id="r_aa49663a5d76af14424c7d1c3525b9381"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aa49663a5d76af14424c7d1c3525b9381">SYSCLKDivider</a></td></tr>
<tr class="memitem:abd9bcaa8dcf4b816462ee2930ab3e993" id="r_abd9bcaa8dcf4b816462ee2930ab3e993"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#abd9bcaa8dcf4b816462ee2930ab3e993">AHBCLKDivider</a></td></tr>
<tr class="memitem:aabb6ee5533a966785511f3d09bcf255d" id="r_aabb6ee5533a966785511f3d09bcf255d"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aabb6ee5533a966785511f3d09bcf255d">APB3CLKDivider</a></td></tr>
<tr class="memitem:a21ceb024102adc3c4dc7eb270cf02ebd" id="r_a21ceb024102adc3c4dc7eb270cf02ebd"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a21ceb024102adc3c4dc7eb270cf02ebd">APB1CLKDivider</a></td></tr>
<tr class="memitem:aa75c110cd93855d49249f38da8cf94f7" id="r_aa75c110cd93855d49249f38da8cf94f7"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aa75c110cd93855d49249f38da8cf94f7">APB2CLKDivider</a></td></tr>
<tr class="memitem:a2ad661dc89d2d18b5e31d7d2c8d33de8" id="r_a2ad661dc89d2d18b5e31d7d2c8d33de8"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a2ad661dc89d2d18b5e31d7d2c8d33de8">APB4CLKDivider</a></td></tr>
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<a name="details" id="details"></a><h2 id="header-details" class="groupheader">Detailed Description</h2>
<div class="textblock"><p>RCC System, AHB and APB busses clock configuration structure definition. </p>
</div><a name="doc-variable-members" id="doc-variable-members"></a><h2 id="header-doc-variable-members" class="groupheader">Member Data Documentation</h2>
<a id="abd9bcaa8dcf4b816462ee2930ab3e993" name="abd9bcaa8dcf4b816462ee2930ab3e993"></a>
<h2 class="memtitle"><span class="permalink"><a href="#abd9bcaa8dcf4b816462ee2930ab3e993">&#9670;&#160;</a></span>AHBCLKDivider</h2>

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          <td class="memname">uint32_t RCC_ClkInitTypeDef::AHBCLKDivider</td>
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<p>The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). This parameter can be a value of <a class="el" href="group___r_c_c___h_c_l_k___clock___source.html">RCC HCLK Clock Source</a> </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a21ceb024102adc3c4dc7eb270cf02ebd">&#9670;&#160;</a></span>APB1CLKDivider</h2>

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          <td class="memname">uint32_t RCC_ClkInitTypeDef::APB1CLKDivider</td>
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<p>The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of <a class="el" href="group___r_c_c___a_p_b1___clock___source.html">RCC APB1 Clock Source</a> </p>

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<a id="aa75c110cd93855d49249f38da8cf94f7" name="aa75c110cd93855d49249f38da8cf94f7"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aa75c110cd93855d49249f38da8cf94f7">&#9670;&#160;</a></span>APB2CLKDivider</h2>

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          <td class="memname">uint32_t RCC_ClkInitTypeDef::APB2CLKDivider</td>
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<p>The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of <a class="el" href="group___r_c_c___a_p_b2___clock___source.html">RCC APB2 Clock Source</a> </p>

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<a id="aabb6ee5533a966785511f3d09bcf255d" name="aabb6ee5533a966785511f3d09bcf255d"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aabb6ee5533a966785511f3d09bcf255d">&#9670;&#160;</a></span>APB3CLKDivider</h2>

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          <td class="memname">uint32_t RCC_ClkInitTypeDef::APB3CLKDivider</td>
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<p>The APB3 clock (D1PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of <a class="el" href="group___r_c_c___a_p_b3___clock___source.html">RCC APB3 Clock Source</a> </p>

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<a id="a2ad661dc89d2d18b5e31d7d2c8d33de8" name="a2ad661dc89d2d18b5e31d7d2c8d33de8"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a2ad661dc89d2d18b5e31d7d2c8d33de8">&#9670;&#160;</a></span>APB4CLKDivider</h2>

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          <td class="memname">uint32_t RCC_ClkInitTypeDef::APB4CLKDivider</td>
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<p>The APB4 clock (D3PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of <a class="el" href="group___r_c_c___a_p_b4___clock___source.html">RCC APB4 Clock Source</a> </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a93a53676a1cfc5b55b8b990e7ff4dac5">&#9670;&#160;</a></span>ClockType</h2>

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          <td class="memname">uint32_t RCC_ClkInitTypeDef::ClockType</td>
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<p>The clock to be configured. This parameter can be a value of <a class="el" href="group___r_c_c___system___clock___type.html">RCC System Clock Type</a> </p>

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<h2 class="memtitle"><span class="permalink"><a href="#aa49663a5d76af14424c7d1c3525b9381">&#9670;&#160;</a></span>SYSCLKDivider</h2>

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<p>The system clock divider. This parameter can be a value of <a class="el" href="group___r_c_c___s_y_s___clock___source.html">RCC SYS Clock Source</a> </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a4ceff1fdbf423e347c63052ca2c1d7e1">&#9670;&#160;</a></span>SYSCLKSource</h2>

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<p>The clock source (SYSCLKS) used as system clock. This parameter can be a value of <a class="el" href="group___r_c_c___system___clock___source.html">RCC System Clock Source</a> </p>

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<hr/>The documentation for this struct was generated from the following file:<ul>
<li>C:/Users/ASUS/Desktop/dm-ctrlH7-balance-9025test/Drivers/STM32H7xx_HAL_Driver/Inc/<a class="el" href="stm32h7xx__hal__rcc_8h_source.html">stm32h7xx_hal_rcc.h</a></li>
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